Sound Byte Libs 29c5ff3
C++ firmware library for audio applications on 32-bit ARM Cortex-M processors
Loading...
Searching...
No Matches
Classes | Functions
sbl::hal::memory Namespace Reference

Classes

struct  ArmMemoryBarrier
 Memory barrier policy for RingBuffer template. More...
 

Functions

void compiler_barrier ()
 Compiler memory barrier.
 
void data_barrier ()
 Data Memory Barrier (ARM DMB instruction)
 
void sync_barrier ()
 Data Synchronization Barrier (ARM DSB instruction)
 
void instruction_barrier ()
 Instruction Synchronization Barrier (ARM ISB instruction)
 

Function Documentation

◆ compiler_barrier()

void sbl::hal::memory::compiler_barrier ( )
inline

Compiler memory barrier.

Prevents compiler from reordering memory operations. Sufficient for single-core ARM Cortex-M systems. Compiles to no instructions - affects compiler optimization only.

Note
ISR-safe — compiler-only barrier, zero instructions

Definition at line 26 of file barrier.hpp.

Referenced by data_barrier(), sbl::hal::memory::ArmMemoryBarrier::full_barrier(), instruction_barrier(), and sync_barrier().

Here is the caller graph for this function:

◆ data_barrier()

void sbl::hal::memory::data_barrier ( )
inline

Data Memory Barrier (ARM DMB instruction)

Ensures all memory operations before the barrier complete before any memory operations after the barrier begin. Compiles to single ARM DMB instruction.

Note
ISR-safe — single DMB instruction

Definition at line 39 of file barrier.hpp.

References compiler_barrier().

Here is the call graph for this function:

◆ instruction_barrier()

void sbl::hal::memory::instruction_barrier ( )
inline

Instruction Synchronization Barrier (ARM ISB instruction)

Flushes pipeline and ensures all subsequent instructions are fetched from cache/memory after barrier effects complete. Compiles to single ARM ISB instruction.

Note
ISR-safe — single ISB instruction

Definition at line 73 of file barrier.hpp.

References compiler_barrier().

Here is the call graph for this function:

◆ sync_barrier()

void sbl::hal::memory::sync_barrier ( )
inline

Data Synchronization Barrier (ARM DSB instruction)

Ensures all memory operations and instructions complete before proceeding. Stronger than DMB. Compiles to single ARM DSB instruction.

Note
ISR-safe — single DSB instruction

Definition at line 56 of file barrier.hpp.

References compiler_barrier().

Here is the call graph for this function: