barrier.hpp

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/**
 * @file barrier.hpp
 * @brief ARM Cortex-M memory barrier primitives
 * @ingroup hal
 * 
 * Direct memory barrier operations for ARM Cortex-M processors.
 * No templates - just hardware primitives that compile to single instructions.
 */
 
#ifndef SBL_HAL_MEMORY_BARRIER_HPP_
#define SBL_HAL_MEMORY_BARRIER_HPP_
 
namespace sbl {
namespace hal {
namespace memory {
 
/**
 * @brief Compiler memory barrier
 * 
 * Prevents compiler from reordering memory operations.
 * Sufficient for single-core ARM Cortex-M systems.
 * Compiles to no instructions - affects compiler optimization only.
 *
 * @note ISR-safe — compiler-only barrier, zero instructions
 */
inline void compiler_barrier() {
    asm volatile("" ::: "memory");
}
 
/**
 * @brief Data Memory Barrier (ARM DMB instruction)
 * 
 * Ensures all memory operations before the barrier complete
 * before any memory operations after the barrier begin.
 * Compiles to single ARM DMB instruction.
 *
 * @note ISR-safe — single DMB instruction
 */
inline void data_barrier() {
#ifdef __ARM_ARCH
    asm volatile("dmb" ::: "memory");
#else
    compiler_barrier();  // Fallback for non-ARM builds
#endif
}
 
/**
 * @brief Data Synchronization Barrier (ARM DSB instruction)
 * 
 * Ensures all memory operations and instructions complete
 * before proceeding. Stronger than DMB.
 * Compiles to single ARM DSB instruction.
 *
 * @note ISR-safe — single DSB instruction
 */
inline void sync_barrier() {
#ifdef __ARM_ARCH
    asm volatile("dsb" ::: "memory");
#else
    compiler_barrier();  // Fallback for non-ARM builds
#endif
}
 
/**
 * @brief Instruction Synchronization Barrier (ARM ISB instruction)
 * 
 * Flushes pipeline and ensures all subsequent instructions
 * are fetched from cache/memory after barrier effects complete.
 * Compiles to single ARM ISB instruction.
 *
 * @note ISR-safe — single ISB instruction
 */
inline void instruction_barrier() {
#ifdef __ARM_ARCH
    asm volatile("isb" ::: "memory");
#else
    compiler_barrier();  // Fallback for non-ARM builds
#endif
}
 
/**
 * @brief Memory barrier policy for RingBuffer template
 *
 * On single-core Cortex-M, a compiler barrier is sufficient for SPSC
 * ring buffers. It prevents the compiler from reordering stores (data
 * write before index update) without emitting any instructions.
 */
struct ArmMemoryBarrier {
    /** @note ISR-safe — compiler-only barrier, zero instructions */
    static void full_barrier() {
        compiler_barrier();
    }
};
 
} // namespace memory
} // namespace hal
} // namespace sbl
 
#endif // SBL_HAL_MEMORY_BARRIER_HPP_