dwt.hpp

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/**
 * @file dwt.hpp
 * @brief DWT cycle counter for ARM Cortex-M7
 *
 * Provides cycle-accurate profiling via the Data Watchpoint and Trace (DWT)
 * unit's CYCCNT register. At 480 MHz (STM32H750), this gives ~2.08 ns
 * resolution with wrap every ~8.9 seconds.
 *
 * IMPORTANT: Cortex-M7 requires unlocking the DWT via the Lock Access
 * Register (LAR) before CYCCNT works. M3/M4 code that omits this step
 * will silently fail on M7 -- writes are ignored, counter never starts.
 *
 * @note DWT is ARM Cortex-M specific. RP2xxx profiling requires a
 *       SysTick or hardware timer fallback (not implemented here).
 */
#pragma once
#ifndef SBL_PROFILING_DWT_HPP
#define SBL_PROFILING_DWT_HPP
#include <cstdint>
 
namespace sbl::profiling {
 
namespace detail {
 
// CoreDebug, DWT register addresses (ARMv7-M Architecture Reference Manual)
inline volatile uint32_t& DEMCR      = *reinterpret_cast<volatile uint32_t*>(0xE000EDFC);
inline volatile uint32_t& DWT_CTRL   = *reinterpret_cast<volatile uint32_t*>(0xE0001000);
inline volatile uint32_t& DWT_CYCCNT = *reinterpret_cast<volatile uint32_t*>(0xE0001004);
inline volatile uint32_t& DWT_LAR    = *reinterpret_cast<volatile uint32_t*>(0xE0001FB0);
 
static constexpr uint32_t TRCENA_BIT    = 1u << 24;
static constexpr uint32_t CYCCNTENA_BIT = 1u << 0;
static constexpr uint32_t LAR_UNLOCK    = 0xC5ACCE55;
 
} // namespace detail
 
/// Initialize DWT cycle counter. Call once after clock configuration.
inline void dwt_init() {
    detail::DEMCR     |= detail::TRCENA_BIT;       // enable trace block
    detail::DWT_LAR    = detail::LAR_UNLOCK;        // M7: unlock DWT regs
    detail::DWT_CYCCNT = 0;                         // reset
    detail::DWT_CTRL  |= detail::CYCCNTENA_BIT;     // start counting
}
 
/// Read current cycle count (free-running, wraps at 2^32).
/// Unsigned subtraction handles wraparound correctly.
inline uint32_t cycles() {
    return detail::DWT_CYCCNT;
}
 
/// RAII scope for measuring a block of code.
/// Usage: volatile uint32_t elapsed; { CycleScope s(elapsed); /* code */ }
struct CycleScope {
    uint32_t start_;
    volatile uint32_t& result_;
 
    explicit CycleScope(volatile uint32_t& out)
        : start_(cycles()), result_(out) {}
    ~CycleScope() { result_ = cycles() - start_; }
};
 
} // namespace sbl::profiling
 
#endif // SBL_PROFILING_DWT_HPP