dwt.hpp File Reference

DWT cycle counter for ARM Cortex-M7. More...

#include <cstdint>

Include dependency graph for dwt.hpp:

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Classes
struct	sbl::profiling::CycleScope

Namespaces
namespace	sbl
	Root namespace for all Sound Byte Libs functionality.
namespace	sbl::profiling
	CPU load monitoring.
namespace	sbl::profiling::detail

Macros
#define	SBL_PROFILING_DWT_HPP

Functions
void	sbl::profiling::dwt_init ()
	Initialize DWT cycle counter. Call once after clock configuration.
uint32_t	sbl::profiling::cycles ()

Variables
volatile uint32_t &	sbl::profiling::detail::DEMCR = *reinterpret_cast<volatile uint32_t*>(0xE000EDFC)
volatile uint32_t &	sbl::profiling::detail::DWT_CTRL = *reinterpret_cast<volatile uint32_t*>(0xE0001000)
volatile uint32_t &	sbl::profiling::detail::DWT_CYCCNT = *reinterpret_cast<volatile uint32_t*>(0xE0001004)
volatile uint32_t &	sbl::profiling::detail::DWT_LAR = *reinterpret_cast<volatile uint32_t*>(0xE0001FB0)
static constexpr uint32_t	sbl::profiling::detail::TRCENA_BIT = 1u << 24
static constexpr uint32_t	sbl::profiling::detail::CYCCNTENA_BIT = 1u << 0
static constexpr uint32_t	sbl::profiling::detail::LAR_UNLOCK = 0xC5ACCE55

Detailed Description

DWT cycle counter for ARM Cortex-M7.

Provides cycle-accurate profiling via the Data Watchpoint and Trace (DWT) unit's CYCCNT register. At 480 MHz (STM32H750), this gives ~2.08 ns resolution with wrap every ~8.9 seconds.

IMPORTANT: Cortex-M7 requires unlocking the DWT via the Lock Access Register (LAR) before CYCCNT works. M3/M4 code that omits this step will silently fail on M7 – writes are ignored, counter never starts.

Note

DWT is ARM Cortex-M specific. RP2xxx profiling requires a SysTick or hardware timer fallback (not implemented here).

Definition in file dwt.hpp.

Macro Definition Documentation

SBL_PROFILING_DWT_HPP

#define SBL_PROFILING_DWT_HPP

Definition at line 18 of file dwt.hpp.